1. Field of the Invention
The invention relates to phase locked loops (PLLs), and more particularly, to a phase locked loop capable of improving stability without greatly increasing chip area thereof.
2. Description of the Related Art
Many different types of integrated circuits (IC) and non-integrated circuits employ clock generating circuits such as phase locked loops (PLL). Some examples of integrated circuits that employ clock generators include, but are not limited to, graphics processors, central processing units, microprocessors, and communication ICs or any other suitable IC that employs clock generators. In order to design a PLL having required characteristics (e.g. low phase noise), a loop filter in the PLL typically requires more than 10 nF of capacitance for stability of the PLL. However, a larger capacitance requires a larger chip area. Hence, there is a need to improve stability of PLLs without greatly increasing chip area.